#include "cfg_drive.h"
#include <main.h>
#include <stdint.h>

// 初始化引脚配置表格和枚举表格一一对应
// 索引不能变
LaserPinConfigSt LaserPinConfigTable[Count] = {
    {CH1_ADS1119_REG_DRDY, CURRENT1_DRDY_Pin, CURRENT1_DRDY_GPIO_Port},
    {CH1_ADS1119_REG_RST, CURRENT1_RESET_Pin, CURRENT1_RESET_GPIO_Port},
    {CH1_ADS1119_REG_SDA, CURRENT1_SDA_Pin, CURRENT1_SDA_GPIO_Port},
    {CH1_ADS1119_REG_SCL, CURRENT1_SCL_Pin, CURRENT1_SCL_GPIO_Port},
    {CH2_ADS1119_REG_DRDY, CURRENT2_DRDY_Pin, CURRENT2_DRDY_GPIO_Port},
    {CH2_ADS1119_REG_RST, CURRENT2_RESET_Pin, CURRENT2_RESET_GPIO_Port},
    {CH2_ADS1119_REG_SCL, CURRENT2_SCL_Pin, CURRENT2_SCL_GPIO_Port},
    {CH2_ADS1119_REG_SDA, CURRENT2_SDA_Pin, CURRENT2_SDA_GPIO_Port},
    {CH1_AD5541_REG_NSS, CURRENT1_NSS_Pin, CURRENT1_NSS_GPIO_Port},
    {CH1_AD5541_REG_SCK, CURRENT1_SCK_Pin, CURRENT1_SCK_GPIO_Port},
    {CH1_AD5541_REG_MOSI, CURRENT1_MOSI_Pin, CURRENT1_MOSI_GPIO_Port},
    {CH2_AD5541_REG_NSS, CURRENT2_NSS_Pin, CURRENT2_NSS_GPIO_Port},
    {CH2_AD5541_REG_SCK, CURRENT2_SCK_Pin, CURRENT2_SCK_GPIO_Port},
    {CH2_AD5541_REG_MOSI, CURRENT2_MOSI_Pin, CURRENT2_MOSI_GPIO_Port},
    {AD7689_REG_NSS, TADC_NSS_M_Pin, TADC_NSS_M_GPIO_Port},
    {AD7689_REG_SCK, TADC_SCK_M_Pin, TADC_SCK_M_GPIO_Port},
    {AD7689_REG_MOSI, TADC_MOSI_M_Pin, TADC_MOSI_M_GPIO_Port},
    {AD7689_REG_MISO, TADC_MISO_M_Pin, TADC_MISO_M_GPIO_Port},
    {CH1_DAC8830_REG_NSS, TDAC1_NSS_M_Pin, TDAC1_NSS_M_GPIO_Port},
    {CH1_DAC8830_REG_SCK, TDAC1_SCK_M_Pin, TDAC1_SCK_M_GPIO_Port},
    {CH1_DAC8830_REG_MOSI, TDAC1_MOSI_M_Pin, TDAC1_MOSI_M_GPIO_Port},
    {CH2_DAC8830_REG_NSS, TDAC2_NSS_M_Pin, TDAC2_NSS_M_GPIO_Port},
    {CH2_DAC8830_REG_SCK, TDAC2_SCK_M_Pin, TDAC2_SCK_M_GPIO_Port},
    {CH2_DAC8830_REG_MOSI, TDAC2_MOSI_M_Pin, TDAC2_MOSI_M_GPIO_Port},
    {UART1_REG_TXD, TX1_Pin, TX1_GPIO_Port},
    {UART1_REG_RXD, RX1_Pin, RX1_GPIO_Port},
    {UART2_REG_DE, USART2_DE_Pin, USART2_DE_GPIO_Port},
    {UART2_REG_TXD, UART_TXD_Pin, UART_TXD_GPIO_Port},
    {UART2_REG_RXD, UART_RDX_Pin, UART_RDX_GPIO_Port},
    {UART3_REG_TXD, TX3_Pin, TX3_GPIO_Port},
    {UART3_REG_RXD, RX3_Pin, RX3_GPIO_Port},
    {CH1_REG_OCP, CURRENT1_OCP_Pin, CURRENT1_OCP_GPIO_Port},
    {CH1_REG_OVP, CURRENT1_OVP_Pin, CURRENT1_OVP_GPIO_Port},
    {CH1_REG_UT, U1_UT_M_Pin, U1_UT_M_GPIO_Port},
    {CH1_REG_OT, U1_OT_M_Pin, U1_OT_M_GPIO_Port},
    {CH2_REG_OCP, CURRENT2_OCP_Pin, CURRENT2_OCP_GPIO_Port},
    {CH2_REG_OVP, CURRENT2_OVP_Pin, CURRENT2_OVP_GPIO_Port},
    {CH2_REG_OT, U2_OT_M_Pin, U2_OT_M_GPIO_Port},
    {CH2_REG_UT, U2_UT_M_Pin, U2_UT_M_GPIO_Port},
    {CH1_REG_LD_EN, LD1_EN_Pin, LD1_EN_GPIO_Port},
    {CH1_REG_LD_ON, LD1_ON_Pin, LD1_ON_GPIO_Port},
    {CH2_REG_LD_EN, LD2_EN_Pin, LD2_EN_GPIO_Port},
    {CH2_REG_LD_ON, LD2_ON_Pin, LD2_ON_GPIO_Port},
    {CH1_REG_SHDN, U1_SHDN_M_Pin, U1_SHDN_M_GPIO_Port},
    {CH2_REG_SHDN, U2_SHDN_M_Pin, U2_SHDN_M_GPIO_Port},
    {CH1_REG_CPTART, CPTART_Pin, CPTART_GPIO_Port},
    {CH2_REG_CPTART, CPSTART1_Pin, CPSTART1_GPIO_Port},
    {EEPROM_WP, EEPROM_WP_Pin, EEPROM_WP_GPIO_Port},
    {LED_1, LED1_Pin, LED1_GPIO_Port},
    {LED_2, LED2_Pin, LED2_GPIO_Port},
    {REG_JTRST, JTRST_Pin, JTRST_GPIO_Port},
};
